The present invention relates to integrated circuits, and more particularly to integrated circuits with isolation trenches that isolate active areas in a semiconductor substrate.
FIG. 1 illustrates a vertical cross section of an integrated circuit in the process of forming self-aligned shallow trench isolation (STI) regions between active areas 110 of a monocrystalline silicon substrate 120. A similar process is disclosed in U.S. Pat. No. 6,355,524 issued Mar. 12, 2002 to Tuan et al. and incorporated herein by reference. The integrated circuit is a flash memory with floating gates. A silicon dioxide layer 130 has been formed on silicon substrate 120. A doped polysilicon layer 140 has been formed on oxide 130 to provide the floating gates. A sacrificial layer 150 of silicon nitride has been formed on polysilicon 130 and patterned photolithographically to define the active areas 110 and isolation trenches 160. Polysilicon 140, oxide 130, and silicon substrate 120 are etched with nitride 150 as a mask to form the trenches. The trenches are filled with silicon dioxide 170, which initially covers the nitride 150 but is then polished off from over the nitride by chemical mechanical polishing (CMP). Oxide 170 provides shallow trench isolation regions isolating the active areas 110 from each other.
Nitride 150 is etched away (FIG. 2A), and oxide 170 may be etched down to provide a more planar structure. FIG. 2B is a top view at this stage, with FIG. 2A corresponding to the vertical cross section along the line A-A′ in FIG. 2B.
As shown in FIG. 3A (vertical cross section marked A-A′ in FIGS. 2B and 3B) and FIG. 3B (top view), dielectric 310 is formed on polysilicon 140 and STI oxide 170. Doped polysilicon 320 is deposited on dielectric 310. Additional layers (not shown) may be deposited on top. Then a mask (not shown) is formed to define the control gates. Layers 320, 310, 140, 130 are etched as defined by that mask to form control gates from polysilicon 320 and to separate adjacent floating gates 140 in each column from each other. STI oxide 170 may be slightly etched in this process. A suitable dopant is implanted to form source/drain regions 330 in substrate 120 on the opposite sides of each control gate line 320.
Improved fabrication techniques are desired.